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5-1 march 1997 hd-6409 cmos manchester encoder-decoder features ? converter or repeater mode ? independent manchester encoder and decoder operation ? static to one megabit/sec data rate guaranteed ? low bit error rate ? digital pll clock recovery ? on chip oscillator ? low operating power: 50mw typical at +5v ? available in 20 lead dual-in-line and 20 pad lcc package description the hd-6409 manchester encoder-decoder (med) is a high speed, low power device manufactured using self-aligned sil- icon gate technology. the device is intended for use in serial data communication, and can be operated in either of two modes. in the converter mode, the med converts non return-to-zero code (nrz) into manchester code and decodes manchester code into nonreturn-to-zero code. for serial data communication, manchester code does not have some of the de?ciencies inherent in nonreturn-to-zero code. for instance, use of the med on a serial line eliminates dc components, provides clock recovery, and gives a relatively high degree of noise immunity. because the med converts the most commonly used code (nrz) to manchester code, the advantages of using manchester code are easily realized in a serial data link. in the repeater mode, the med accepts manchester code input and reconstructs it with a recovered clock. this mini- mizes the effects of noise on a serial data link. a digital phase lock loop generates the recovered clock. a maximum data rate of 1mhz requires only 50mw of power. manchester code is used in magnetic tape recording and in ?ber optic communication, and generally is used where data accuracy is imperative. because it frames blocks of data, the hd-6409 easily interfaces to protocol controllers. pinouts hd-6409 (cerdip, pdip, soic) top view hd-6409 (clcc) top view ordering information package temperature range 1 megabit/sec pkg. no. pdip -40 o c to +85 o c hd3-6409-9 e20.3 soic -40 o c to +85 o c hd9p6409-9 m20.3 cerdip -40 o c to +85 o c hd1-6409-9 f20.3 desc -55 o c to 125 o c 5962-9088801mra f20.3 clcc -40 o c to +85 o c HD4-6409-9 j20.a desc -55 o c to 125 o c 5962-9088801m2a j20.a 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bzi boi udi sd/cds sdo srst dclk nvm rst gnd v cc bzo ss eclk boo cts ms ox ix co sd/cds sdo srst nvm dclk udi boi bzi v cc boo rst gnd co ix ox bzo ss eclk cts ms 4 5 6 7 8 10 11 12 13 9 3212019 16 17 18 15 14 file number 2951.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
5-2 block diagram logic symbol edge detector command sync generator output select logic boi bzi udi rst sd/cds ix ox co ss reset 5-bit shift register and decoder data input logic input/ output select oscillator counter circuits manchester encoder sdo nvm boo bzo cts srst ms eclk dclk sd clock generator encoder control decoder ss co sd/cds eclk ms rst sdo dclk nvm srst ox ix boo bzo cts boi bzi udi 13 12 19 18 15 2 1 3 17 11 4 16 14 8 7 6 5 9 hd-6409
5-3 pin description pin number type symbol name description 1 i bzl bipolar zero input used in conjunction with pin 2, bipolar one input (bol), to input manchester ii encoded data to the decoder, bzi and bol are logical complements. when using pin 3, unipolar data input (udi) for data input, bzi must be held high. 2 i bol bipolar one input used in conjunction with pin 1, bipolar zero input (bzi), to input manchester ii encoded data to the decoder, boi and bzi are logical complements. when using pin 3, unipolar data input (udi) for data input, bol must be held low. 3 i udi unipolar data input an alternate to bipolar input (bzl, bol), unipolar data input (udl) is used to input manchester ii encoded data to the decoder. when using pin 1 (bzl) and pin 2 (bol) for data input, udi must be held low. 4 i/o sd/cds serial data/com- mand data sync in the converter mode, sd/cds is an input used to receive serial nrz data. nrz data is accepted synchronously on the falling edge of encoder clock output (eclk). in the repeater mode, sd/cds is an output indicating the status of last valid sync pattern received. a high indicates a command sync and a low indicates a data sync pattern. 5 o sdo serial data out the decoded serial nrz data is transmitted out synchronously with the decoder clock (dclk). sdo is forced low when rst is low. 6o srst ser ial reset in the converter mode, srst follows rst. in the repeater mode, when rst goes low, srst goes low and remains low after rst goes high. srst goes high only when rst is high, the reset bit is zero, and a valid synchronization sequence is received. 7o nvm non v alid manchester a low on nvm indicates that the decoder has received invalid manchester data and present data on serial data out (sdo) is invalid. a high indicates that the sync pulse and data were valid and sdo is valid. nvm is set low by a low on rst, and remains low after rst goes high until valid sync pulse followed by two valid manchester bits is received. 8 o dclk decoder clock the decoder clock is a 1x clock recovered from bzl and bol, or udi to synchro- nously output received nrz data (sdo). 9i rst reset in the converter mode, a low on rst forces sdo, dclk, nvm, and srst low. a high on rst enables sdo and dclk, and forces srst high. nvm remains low after rst goes high until a valid sync pulse followed by two manchester bits is received, after which it goes high. in the repeater mode, rst has the same ef- fect on sdo, dclk and nvm as in the converter mode. when rst goes low, srst goes low and remains low after rst goes high. srst goes high only when rst is high, the reset bit is zero and a valid synchronization sequence is received. 10 i gnd ground ground 11 o c o clock output buffered output of clock input i x . may be used as clock signal for other peripherals. 12 i i x clock input i x is the input for an external clock or, if the internal oscillator is used, i x and o x are used for the connection of the crystal. 13 o o x clock drive if the internal oscillator is used, o x and i x are used for the connection of the crys- tal. 14 i ms mode select ms must be held low for operation in the converter mode, and high for operation in the repeater mode. 15 i cts clear to send in the converter mode, a high disables the encoder, forcing outputs boo, bzo high and eclk low. a high to low transition of cts initiates transmission of a command sync pulse. a low on cts enables boo, bzo, and eclk. in the repeater mode, the function of cts is identical to that of the converter mode with the exception that a transition of cts does not initiate a synchronization sequence. 16 o eclk encoder clock in the converter mode, eclk is a 1x clock output used to receive serial nrz data to sd/cds. in the repeater mode, eclk is a 2x clock which is recovered from bzl and bol data by the digital phase locked loop. hd-6409
5-4 encoder operation the encoder uses free running clocks at 1x and 2x the data rate derived from the system clock l x for internal timing. cts is used to control the encoder outputs, eclk, boo and bzo. a free running 1x eclk is transmitted out of the encoder to drive the external circuits which supply the nrz data to the med at pin sd/cds. a low on cts enables encoder outputs eclk, boo and bzo, while a high on cts forces bzo, boo high and holds eclk low. when cts goes from high to low , a synchro- nization sequence is transmitted out on boo and bzo. a synchronization sequence consists of eight manchester 0 bits followed by a command sync pulse. a command sync pulse is a 3-bit wide pulse with the ?rst 1 1/2 bits high followed by 1 1/2 bits low. serial nrz data is clocked into the encoder at sd/cds on the high to low transition of eclk during the command sync pulse. the nrz data received is encoded into manchester ii data and transmitted out on boo and bzo following the command sync pulse. fol- lowing the synchronization sequence, input data is encoded and transmitted out continuously without parity check or word framing. the length of the data block encoded is de?ned by cts. manchester data out is inverted. decoder operation the decoder requires a single clock with a frequency 16x or 32x the desired data rate. the rate is selected on the speed select with ss low producing a 16x clock and high a 32x clock. for long data links the 32x mode should be used as this permits a wider timing jitter margin. the internal opera- tion of the decoder utilizes a free running clock synchronized with incoming data for its clocking. the manchester ii encoded data can be presented to the decoder in either of two ways. the bipolar one and bipolar zero inputs will accept data from differential inputs such as a comparator sensed transformer coupled bus. the unipolar data input can only accept noninverted manchester ii encoded data i.e. bipolar one out through an inverter to unipolar data input. the decoder continuously monitors this data input for valid sync pattern. note that while the med encoder section can generate only a command sync pattern, the decoder can recognize either a command or data sync pattern. a data sync is a logically inverted command sync. 17 i ss speed select a logic high on ss sets the data rate at 1/32 times the clock frequency while a low sets the data rate at 1/16 times the clock frequency. 18 o bzo bipolar zero output bzo and its logical complement boo are the manchester data outputs of the en- coder. the inactive state for these outputs is in the high state. 19 o boo bipolar one out see pin 18. 20 i v cc v cc v cc is the +5v power supply pin. a 0.1 m f decoupling capacitor from v cc (pin- 20) to gnd (pin-10) is recommended. note: (i) input (o) output pin description pin number type symbol name description 1 2 3 4 1 2 3 4 cts eclk sd/cds bzo boo t ce6 0 000 00 00 t ce5 synchronization sequence eight 0s command sync dont care 1 0 1 1 0 1 figure 1. encoder operation hd-6409
5-5 there is a three bit delay between udi, bol, or bzi input and the decoded nrz data transmitted out of sdo. control of the decoder outputs is provided by the rst pin. when rst is low, sdo, dclk and nvm are forced low. when rst is high, sdo is transmitted out synchronously with the recovered clock dclk. the nvm output remains low after a low to high transition on rst until a valid sync pattern is received. the decoded data at sdo is in nrz format. dclk is pro- vided so that the decoded bits can be shifted into an external register on every high to low transition of this clock. three bit periods after an invalid manchester bit is received on udi, or bol, nvm goes low synchronously with the questionable data output on sdo. further, the decoder does not reestablish proper data decoding until another sync pattern is recognized. repeater operation manchester il data can be presented to the repeater in either of two ways. the inputs bipolar one in and bipolar zero in will accept data from differential inputs such as a comparator or sensed transformer coupled bus. the input unipolar data in accepts only noninverted manchester ii coded data. the decoder requires a single clock with a frequency 16x or 32x the desired data rate. this clock is selected to 16x with speed select low and 32x with speed select high. for long data links the 32x mode should be used as this permits a wider timing jitter margin. the inputs udl, or bol, bzl are delayed approximately 1/2 bit period and repeated as outputs boo and bzo. the 2x eclk is transmitted out of the repeater synchronously with boo and bzo. a low on cts enables eclk, boo, and bzo. in contrast to the converter mode, a transition on cts does not initiate a synchronization sequence of eight 0s and a command sync. the repeater mode does recognize a command or data sync pulse. sd/cds is an output which re?ects the state of the most recent sync pulse received, with high indicating a com- mand sync and low indicating a data sync. when rst is low, the outputs sdo, dclk, and nvm are low, and srst is set low. srst remains low after rst goes high and is not reset until a sync pulse and two valid manchester bits are received with the reset bit low. the reset bit is the ?rst data bit after the sync pulse. with rst high, nrz data is transmitted out of serial data out synchro- nously with the 1x dclk. figure 2. decoder operation dclk udi sdo rst nvm command sync 1001010101010 figure 3. repeater operation input count eclk udi bzo boo rst srst sync pulse 1 2 34 567 hd-6409
5-6 manchester code nonreturn-to-zero (nrz) code represents the binary values logic-o and iogic-1 with a static level maintained throughout the data cell. in contrast, manchester code represents data with a level transition in the middle of the data cell. manches- ter has bandwidth, error detection, and synchronization advantages over nrz code. the manchester ii code bipolar one and bipolar zero shown below are logical complements. the direction of the transi- tion indicates the binary value of data. a logic-0 in bipolar one is de?ned as a low to high transition in the middle of the data cell, and a logic-1 as a high to low mid bit transition, manchester il is also known as biphase-l code. the bandwidth of nrz is from dc to the clock frequency fc/2, while that of manchester is from fc/2 to fc. thus, manchester can be ac or transformer coupled, which has considerable advantages over dc coupling. also, the ratio of maximum to minimum frequency of manchester extends one octave, while the ratio for nrz is the range of 5-10 octaves. it is much eas- ier to design a narrow band than a wideband amp. secondly, the mid bit transition in each data cell provides the code with an effective error detection scheme. if noise pro- duces a logic inversion in the data cell such that there is no transition, an error indiction is given, and synchronization must be re-established. this places relatively stringent requirements on the incoming data. the synchronization advantages of using the hd-6409 and manchester code are several fold. one is that manchester is a self clocking code. the clock in serial data communication de?nes the position of each data cell. non self clocking codes, as nrz, often require an extra clock wire or clock track (in magnetic recording). further, there can be a phase variation between the clock and data track. crosstalk between the two may be a problem. in manchester, the serial data stream contains both the clock and the data, with the position of the mid bit transition representing the clock, and the direction of the transition representing data. there is no phase variation between the clock and the data. a second synchronization advantage is a result of the num- ber of transitions in the data. the decoder resynchronizes on each transition, or at least once every data cell. in contrast, receivers using nrz, which does not necessarily have tran- sitions, must resynchronize on frame bit transitions, which occur far less often, usually on a character basis. this more frequent resynchronization eliminates the cumulative effect of errors over successive data cells. a ?nal synchronization advantage concerns the hd-6409s sync pulse used to ini- tiate synchronization. this three bit wide pattern is suf?- ciently distinct from manchester data that a false start by the receiver is unlikely. crystal oscillator mode figure 5. crystal oscillator mode lc oscillator mode figure 6. lc oscillator mode figure 4. manchester code bit period binary code nonreturn to zero bipolar one bipolar zero 123 45 011 00 i x o x x1 r1 c0 16mhz c1 c1 c o c1 = 32pf c0 = crystal + stray x1 = at cut parallel resonance fundamental mode r s (typ) = 30 w r1 = 15m w c1 c1 l c e c1 2c0 C 2 ------------------------- - ? f o 1 2 p lc e ----------------------- ? c1 = 20pf c0 = 5pf i x o x hd-6409
5-7 using the 6409 as a manchester encoded uart v cc boo bzo ss eclk cts ms ox ix co bzi boi udi sd/cds sdo srst nvm dclk rst gnd bipolar out bipolar out cts lo ad lo ad qh ck si 165 lo ad qh ck 165 bqh a 164 bck a 164 ck data in 273 data in 273 cp reset bipolar in bipolar in figure 7. manchester encoder uart parallel data out parallel data in hd-6409
5-8 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input, output or i/o voltage . . . . . . . . . . . gnd -0.5v to v cc +0.5v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance (typical) q ja q jc cerdip . . . . . . . . . . . . . . . . . . . . . . . . . . 83 o c/w 23 o c/w clcc package . . . . . . . . . . . . . . . . . . . . 95 o c/w 26 o c/w pdip package . . . . . . . . . . . . . . . . . . . . . 75 o c/w n/a soic package . . . . . . . . . . . . . . . . . . . . . 100 o c/w n/a storage temperature range . . . . . . . . . . . . . . . . . .-65 o c to +150 o c maximum junction temperature ceramic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . +300 o c ( lead tips only for surface mount packages) die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 gates caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. operating conditions operating temperature range . . . . . . . . . . . . . . . . . -40 o c to +85 o c operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . .50ns max sync. transition span (t2) . . . . . . . . . . 1.5 dbp typical, (notes 1, 2) short data transition span (t4). . . . . . .0.5dbp typical, (notes 1, 2) long data transition span (t5) . . . . . . .1.0dbp typical, (notes 1, 2) zero crossing tolerance (tcd5) . . . . . . . . . . . . . . . . . . . . . .(note 3) notes: 1. dbp-data bit period, clock rate = 16x, one dbp = 16 clock cycles; clock rate = 32x, one dbp = 32 clock cycles. 2. the input conditions specified are nominal values, the actual input waveforms transition spans may vary by 2 i x clock cycles (16x mode) or 6 i x clock cycles (32x mode). 3. the maximum zero crossing tolerance is 2 i x clock cycles (16x mode) or 6 i x clock cycles (32 mode) from the nominal. dc electrical speci?cations v cc = 5.0v 10%, t a = -40 o c to +85 o (hd-6409-9) symbol parameter min max units (note 1) test conditions v ih logical 1 input voltage 70% v cc -vv cc = 4.5v v il logical 0 input voltage - 20% v cc vv cc = 4.5v v ihr logic 1 input voltage ( reset) v cc -0.5 - v v cc = 5.5v v ilr logic 0 input voltage ( reset) - gnd +0.5 v v cc = 4.5v v ihc logical 1 input voltage (clock) v cc -0.5 - v v cc = 5.5v v ilc logical 0 input voltage (clock) - gnd +0.5 v v cc = 4.5v i i input leakage current (except i x ) -1.0 +1.0 m av in = v cc or gnd, v cc = 5.5v i i input leakage current (i x ) -20 +20 m av in = v cc or gnd, v cc = 5.5v i o i/o leakage current -10 +10 m av out = v cc or gnd, v cc = 5.5v v oh output high voltage (all except o x )v cc -0.4 - v i oh = -2.0ma, v cc = 4.5v (note 2) v ol output low voltage (all except o x ) - 0.4 v i ol = +2.0ma, v cc = 4.5v (note 2) i ccsb standby power supply current - 100 m av in = v cc or gnd, v cc = 5.5v, outputs open i ccop operating power supply current - 18.0 ma f = 16.0mhz, v in = v cc or gnd v cc = 5.5v, c l = 50pf f t functional test - - - (note 1) notes: 1. tested as follows: f = 16mhz, v ih = 70% v cc , v il = 20% v cc , v oh 3 v cc /2, and v ol v cc /2, v cc = 4.5v and 5.5v. 2. interchanging of force and sense conditions is permitted capacitance t a = +25 o c, frequency = 1mhz symbol parameter typ units test conditions c in input capacitance 10 pf all measurements are referenced to device gnd c out output capacitance 12 pf hd-6409
5-9 ac electrical speci?cations v cc = 5.0v 10%, t a = -40 o c to +85 o c (hd-6409-9) symbol parameter min max units (note 1) test conditions f c clock frequency - 16 mhz - t c clock period 1/f c - sec - t 1 bipolar pulse width t c +10 - ns - t 3 one-zero overlap - t c -10 ns - t ch clock high time 20 - ns f = 16.0mhz t cl clock low time 20 - ns f = 16.0mhz t ce1 serial data setup time 120 - ns - t ce2 serial data hold time 0 - ns - t cd2 dclk to sdo, nvm - 40 ns - t r2 eclk to bzo - 40 ns - t r output rise time (all except clock) - 50 ns from 1.0v to 3.5v, c l = 50pf, note 2 t f output fall time (all except clock) - 50 ns from 3.5v to 1.0v, c l = 50pf, note 2 t r clock output rise time - 11 ns from 1.0v to 3.5v, c l = 20pf, note 2 t f clock output fall time - 11 ns from 3.5v to 1.0v, c l = 20pf, note 2 t ce3 eclk to bzo, boo 0.5 1.0 dbp notes 2, 3 t ce4 cts low to bzo, boo enabled 0.5 1.5 dbp notes 2, 3 t ce5 cts low to eclk enabled 10.5 11.5 dbp notes 2, 3 t ce6 cts high to eclk disabled - 1.0 dbp notes 2, 3 t ce7 cts high to bzo, boo disabled 1.5 2.5 dbp notes 2, 3 t cd1 udi to sdo, nvm 2.5 3.0 dbp notes 2, 3 t cd3 rst low to cdlk, sdo, nvm low 0.5 1.5 dbp notes 2, 3 t cd4 rst high to dclk, enabled 0.5 1.5 dbp notes 2, 3 t r1 udi to bzo, boo 0.5 1.0 dbp notes 2, 3 t r3 udi to sdo, nvm 2.5 3.0 dbp notes 2, 3 notes: 1. ac testing as follows: f = 4.0mhz, v ih = 70% v cc , v il = 20% v cc , speed select = 16x, v oh 3 v cc /2, v ol v cc /2, v cc = 4.5v and 5.5v. input rise and fall times driven at 1ns/v, output load = 50pf. 2. guaranteed via characteristics at initial device design and after major process and/or design changes, not tested. 3. dbp-data bit period, clock rate = 16x, one dbp = 16 clock cycles; clock rate = 32x, one dbp = 32 clock cycles. hd-6409
5-10 timing waveforms figure 8. figure 9. clock timing figure 10. output waveform data sync bit period bit period bit period t 2 command sync t 2 t 3 t 3 t 2 t 2 t 4 one one zero t 1 t 1 t 1 t 3 t 3 t 1 t 1 t 1 t 3 t 3 t 3 t 3 t 1 t 4 t 5 t 5 t 2 t 2 command sync t 2 t 2 t 4 t 5 t 5 t 4 t 4 zero one one one data sync boi bzi boi bzi boi bzi udi udi udi t 3 note: udi = 0, for next diagrams note: boi = 0, bzi = 1 for next diagrams t c t ch t r t cl t f 10% 90% t r t f 1.0v 3.5v hd-6409
5-11 figure 11. encoder timing figure 12. encoder timing figure 13. encoder timing note: manchester data-in is not synchronous with decoder clock. decoder clock is synchronous with decoded nrz out of sdo. figure 14. decoder timing figure 15. decoder timing figure 16. decoder timing timing waveforms (continued) eclk sd/cds bzo boo t ce1 t ce2 t ce3 t ce5 t ce4 cts bzo boo eclk t ce6 cts bzo boo eclk t ce7 dclk udi sdo nvm manchester logic-1 manchester logic-0 manchester logic-0 manchester logic-1 t cd2 t cd5 t cd2 t cd1 nrz logic-1 rst dclk, sdo, nvm 50% 50% t cd3 rst dclk 50% t cd4 hd-6409
5-12 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 test load circuit figure 17. repeater timing timing waveforms (continued) udi eclk bzo sdo nvm manchester 1 t r2 t r3 t r3 t r2 t r1 manchester 0 manchester 0 manchester 1 manchester 1 manchester 0 manchester 0 figure 18. test load circuit dut c l (note) note: includes stray and jig capacitance hd-6409

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